数字后端工程师 30-60万

职责描述：
1. Work with Frontend team to understand chip architecture and drive physical aspects early in design cycle;
2. Design automation; Modify and enhance the physical implementation flows;
3. Finish all implementation job and signoff checks, including block level / full chip floor planning, partition, timing closure, place route, power analysis, physical verification etc;

任职要求：
1. 3 years+ of physical design experience in 28/16nm and below technology, bachelor or above, master degree is preferred;
2. Expert in top /block level P&R implementation, including floorplanning, clock & power distribution, timing closure, physical & electrical verification;
3. Experienced with ASIC design flow, hierarchical physical design strategies, and methodologies and understand deep sub-micron technology issues;
4. Proficiency in the Shell/TCL/Perl/Python language and the establishment of automated design process;
5. Experience with DDR block is a plus;
6. Project experience on hierarchical flow such as top-level partition, timing budgeting, pin assignment and Power Network Planning etc is a strong plus;
7. Strong experience in low power design methodology e.g. Power gating, DVFS, etc is a plus;
8. Experience in methodology of Finfet technology is a plus;
9. Self-driven and team-work spirit, strong verbal and written communication skills in Chinese and English.

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