版图工程师（模电/硅光） 30-40万

1.5+ years’ experience in high performance analog layout in advanced CMOS process (28nm or smaller geometry CMOS, deep metal stack, high frequency design >1 GHz) 
2.Experience with layout of high-performance analog IP blocks such as TIA, DAC/ADC, etc. highly desired
3.Thorough knowledge with industry standard EDA tools such as Cadence Virtuoso; extensive experience with DRC, LVS tools and debug verification process
4.Experience with floor planning, block level routing and top level chip assembly
5.Knowledge of high performance analog layout techniques such as common centroid layout, shielding, use of dummy devices
6.Experienced in robust power/signal routing and EM analysis 
7.Strong communicator, works well independently and in team situations
Experience in working with distributed design teams a plus

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