IC Substrate Designer 30-50万

Job Requirements: 
•Mechanical test vehicle design, to support product qualification 
•SIP substrate Layout design and tape out. 
•Skills in Cadence SiP software and layout Symbol Generation/validation. 
•Good knowledge base in the areas of signal integrity and power integrity.
•Familiar laminate substrate processes, stack-up, design rules and laminate supplier chain
•Coordinating DRC review with suppliers and making sure of design for manufacture 
•Generating and maintain product mechanical documentation/application note; 
•Responsible for establishing a commitment to team work and customers
•Good speaking English and communication skills

Minimum Qualifications 
•Bachelor's Degree in EE/ME engineering or equivalent combination of education and experience 
•A minimum of 5 years of relevant semiconductor packaging substrate design experience 
•Experience using Cadence SiP package design tools is required 
•Signal Integrity / Power Integrity (SI/PI) experience is preferred 
•Experience with Si interposer and 3D package design is a plus 
•Experience in programming language(C/C++) or scripting language is a plus 
•Excellent communication and project management skills are required 
•Self-motivated and team oriented with the ability to meet aggressive schedules 
•Demonstrated ability to efficiently complete tasks with minimal supervision 
•Must be very detail oriented, organized and able to work well in a team environment 

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